This invention relates to an amplifier arrangement being provided with a differential pair comprising at least a first and a second transistor of a first conductivity type and with a first main electrode of the first transistor and a first main electrode of the second transistor mutually coupled and coupled to a first supply terminal by means of a current source. A control electrode of the first transistor being coupled to an input terminal and a control electrode of the second transistor is coupled to an output terminal. A current mirror included which comprises at least a third and a fourth transistor of a second conductivity type. A first main electrode of the third transistor and a first main electrode of the fourth transistor are mutually coupled and coupled to a second supply terminal by means of a common terminal. A second main electrode of the third transistor is coupled to a second main electrode of the first transistor and a second main electrode of the fourth transistor is coupled to a second main electrode of the second transistor. A buffer stage comprises at least a fifth transistor of the first conductivity type with a control electrode of the fifth transistor with coupled to the second main electrode of the second transistor, a first main electrode of the fifth transistor with coupled to the output terminal and a second main electrode of the fifth transistor with coupled to the second supply terminal.
Such an amplifier arrangement can be widely used and, more specifically, as a voltage-to-current converter in integrated semiconductor circuits.
An amplifier arrangement of the described type is known from U.S. Pat. 4,338,527.
In this known amplifier arrangement the input terminal is connected to a grounded voltage source and the first and second supply terminals are connected to a negative and a positive supply voltage, respectively. Furthermore, the mutually coupled control electrodes of the third and fourth transistors are connected to the mutually coupled second main electrodes of the first and third transistors so that the second main electrode of the first transistor is adjusted to a voltage equal to the positive supply voltage minus the voltage between the second main electrode and the control electrode of the third transistor. The second main electrode of the second transistor, however, disregarding the offset voltage between the input terminal and the output terminal, is adjusted to a voltage equal to the voltage on the input terminal augmented by the voltage between the second main electrode and the control electrode of the fifth transistor. A disadvantage of this known amplifier arrangement is that with an arbitrary choice of the two supply voltages there is a voltage difference between the respective voltages on the second main electrodes of the first and second transistors. As a result the differential pair is adjusted asymmetrically and, consequently, an undesired non-linear signal transmission from the input terminal to the output terminal takes place. In addition, this disadvantage is enhanced because the voltage on the second main electrode of the first transistor varies with variations of the positive supply voltage, whereas the voltage on the second main electrode of the second transistor does not substantially vary in that case.